/* ==============================================================================
Project Name	: 6-Axis controller for robotic arm with 3 phase motor

Model Number	: FD0B065 v2

File Name		: DeviceInit.c

Description		: Handles MCU peripheral initialization at startup.

=================================================================================
 History:

 Date			Version			Remarks
---------------------------------------------------------------------------------

============================================================================== */

/*** INCLUDES ******************************************************************/
#include "Settings.h"
#include "F28x_Project.h"
#include "DeviceInit.h"


/*** DEFINES *******************************************************************/
#define	ADC_SAMPLING_WINDOW_SIZE		19								// 20 SYSCLK cycles (100ns @SYSCLK=200MHz)


/*** FUNCTIONS *****************************************************************/
void Init_Adc(void)
{
	EALLOW;

	/* Configure ADC-A */
	AdcaRegs.ADCCTL2.bit.PRESCALE    = 6; 								// Set ADC-A ADCCLK divider to /4
    AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);	// 12-bit resolution, single-ended signaling mode
    AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;								// Late interrupt mode
    AdcaRegs.ADCCTL1.bit.ADCPWDNZ    = 1;								// Power up the ADC module

	/* Configure ADC-B */
	AdcbRegs.ADCCTL2.bit.PRESCALE 	 = 6; 								// Set ADC-B ADCCLK divider to /4
    AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);	// 12-bit resolution, single-ended signaling mode
    AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;								// Late interrupt mode
    AdcbRegs.ADCCTL1.bit.ADCPWDNZ    = 1;								// Power up the ADC module

	/* Configure ADC-C */
	AdccRegs.ADCCTL2.bit.PRESCALE 	 = 6; 								// Set ADC-C ADCCLK divider to /4
    AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);	// 12-bit resolution, single-ended signaling mode
    AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;								// Late interrupt mode
    AdccRegs.ADCCTL1.bit.ADCPWDNZ    = 1;								// Power up the ADC module

	/* Configure ADC-D */
	AdcdRegs.ADCCTL2.bit.PRESCALE 	 = 6; 								// Set ADC-D ADCCLK divider to /4
    AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);	// 12-bit resolution, single-ended signaling mode
    AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;								// Late interrupt mode
    AdcdRegs.ADCCTL1.bit.ADCPWDNZ    = 1;								// Power up the ADC module

    /* Delay 1ms to let all ADC modules to power up */
    DELAY_US(1000);

    /* Configure SOCs */
    // ADC-A, SOC0: IFB-U1M
	AdcaRegs.ADCSOC0CTL.bit.CHSEL 	= 0;								// Connect to pin ADCINA0
	AdcaRegs.ADCSOC0CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-A, SOC1: IFB-V1M
	AdcaRegs.ADCSOC1CTL.bit.CHSEL 	= 1;								// Connect to pin ADCINA1
	AdcaRegs.ADCSOC1CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-A, SOC2: IFB-U2M
	AdcaRegs.ADCSOC2CTL.bit.CHSEL 	= 2;								// Connect to pin ADCINA2
	AdcaRegs.ADCSOC2CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-A, SOC3: IFB-V2M
	AdcaRegs.ADCSOC3CTL.bit.CHSEL 	= 3;								// Connect to pin ADCINA3
	AdcaRegs.ADCSOC3CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-B, SOC0: IFB-U3M
	AdcbRegs.ADCSOC0CTL.bit.CHSEL 	= 0;								// Connect to pin ADCINB0
	AdcbRegs.ADCSOC0CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-B, SOC1: IFB-V3M
	AdcbRegs.ADCSOC1CTL.bit.CHSEL 	= 1;								// Connect to pin ADCINB1
	AdcbRegs.ADCSOC1CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-B, SOC2: IFB-U4M
	AdcbRegs.ADCSOC2CTL.bit.CHSEL 	= 2;								// Connect to pin ADCINB2
	AdcbRegs.ADCSOC2CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-B, SOC3: IFB-V4M
	AdcbRegs.ADCSOC3CTL.bit.CHSEL 	= 3;								// Connect to pin ADCINB3
	AdcbRegs.ADCSOC3CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-C, SOC2: HV-SENSEM
	AdccRegs.ADCSOC2CTL.bit.CHSEL 	= 2;								// Connect to pin ADCINC2
	AdccRegs.ADCSOC2CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-D, SOC0: IFB-U5M
	AdcdRegs.ADCSOC0CTL.bit.CHSEL 	= 0;								// Connect to pin ADCIND0
	AdcdRegs.ADCSOC0CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-D, SOC1: IFB-V5M
	AdcdRegs.ADCSOC1CTL.bit.CHSEL 	= 1;								// Connect to pin ADCIND1
	AdcdRegs.ADCSOC1CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-D, SOC2: IFB-U6M
	AdcdRegs.ADCSOC2CTL.bit.CHSEL 	= 2;								// Connect to pin ADCIND2
	AdcdRegs.ADCSOC2CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = 0;								// Software trigger

    // ADC-D, SOC3: IFB-V6M
	AdcdRegs.ADCSOC3CTL.bit.CHSEL 	= 3;								// Connect to pin ADCIND3
	AdcdRegs.ADCSOC3CTL.bit.ACQPS 	= ADC_SAMPLING_WINDOW_SIZE;			// Sampling window size
//	AdcdRegs.ADCSOC3CTL.bit.TRIGSEL = 5;								// Trigger on ePWM1 SOCA
	AdcdRegs.ADCSOC3CTL.bit.TRIGSEL = 0;								// Software trigger


	/* Configure interrupts */
	AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 3; 								// EOC3 will trigger ADCINT1
	AdcaRegs.ADCINTSEL1N2.bit.INT1E   = 1;   							// Enable ADCINT1
	AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; 								// Clear the ADCINT1 flag

//	AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 3; 								// EOC3 will trigger ADCINT1
//	AdcbRegs.ADCINTSEL1N2.bit.INT1E   = 1;   							// Enable ADCINT1
//	AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; 								// Clear the ADCINT1 flag

//	AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 2; 								// EOC2 will trigger ADCINT1
//	AdccRegs.ADCINTSEL1N2.bit.INT1E   = 1;   							// Enable ADCINT1
//	AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; 								// Clear the ADCINT1 flag

//	AdcdRegs.ADCINTSEL1N2.bit.INT1SEL = 3; 								// EOC3 will trigger ADCINT1
//	AdcdRegs.ADCINTSEL1N2.bit.INT1E   = 1;   							// Enable ADCINT1
//	AdcdRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; 								// Clear the ADCINT1 flag

    EDIS;
}


void Init_ePWM1 (void)
{
	InitEPwm1Gpio();

	// Configure Time Base submodule
	EPwm1Regs.TBCTL.bit.CTRMODE 	= TB_COUNT_UP; 						// Count up
	EPwm1Regs.TBPRD 				= EPWM1_TIMER_TBPRD;       			// Set timer period
	EPwm1Regs.TBCTL.bit.PHSEN 		= TB_DISABLE;    					// Disable phase loading
	EPwm1Regs.TBPHS.bit.TBPHS 		= 0x0000;       					// Phase is 0
	EPwm1Regs.TBCTR 				= 0x0000;                  			// Clear counter
	EPwm1Regs.TBCTL.bit.HSPCLKDIV 	= TB_DIV2;   						// TBCLK divider, TBCLK runs at 50MHz
	EPwm1Regs.TBCTL.bit.CLKDIV 		= TB_DIV1;							//

	// Configure Counter-Compare submodule
	EPwm1Regs.CMPA.bit.CMPA 		= EPWM1_PULSE_PERIOD;    			// Set CMPA value
	EPwm1Regs.CMPCTL.bit.SHDWAMODE 	= CC_SHADOW;						// Set CMPA in shadow mode
	EPwm1Regs.CMPCTL.bit.LOADAMODE 	= CC_CTR_ZERO;						// Load CMPA value from shadow register to active register when TBCTR = 0

	// Configure Action Qualifier submodule
	EPwm1Regs.AQCTLA.bit.ZRO 		= AQ_SET;            				// Set EPWM1A pin to HIGH when TBCTR = 0
	EPwm1Regs.AQCTLA.bit.CAU 		= AQ_CLEAR;          				// Set EPWM1A pin to LOW when TBCTR = CMPA on up count

	// Configure Dead-Band submodule
	EPwm1Regs.DBCTL.bit.OUT_MODE	= DB_DISABLE;						// Bypass the deadband submodule
	EPwm1Regs.DBCTL.bit.OUTSWAP		= DB_DISABLE;						// Disable output swap

	// Configure PWM Chopper submodule
	EPwm1Regs.PCCTL.bit.CHPEN		= CHP_DISABLE;						// Disable PWM chopper

	// Event Trigger and Interrupt
	EPwm1Regs.ETSEL.bit.INTSEL 		= ET_CTR_ZERO;     					// Interrupt triggers when TBCTR = 0
	EPwm1Regs.ETPS.bit.INTPRD 		= ET_1ST;           				// Generate interrupt on the first event
	EPwm1Regs.ETSEL.bit.INTEN 		= 1;                				// Enable interrupt
	EPwm1Regs.ETSEL.bit.SOCASEL		= ET_CTR_ZERO;						// EPWM1SOCA pulse will generate when TBCTR = 0
	EPwm1Regs.ETPS.bit.SOCAPRD		= ET_1ST;							// The SOCA pulse will be generated on the first event
	EPwm1Regs.ETSEL.bit.SOCAEN		= 1;								// Enable SOCA pulse generation
	EPwm1Regs.ETCLR.bit.SOCA 		= 1;       							// Clear SOCA flag

	// Enable Group 3 INT1 for EPWM1 interrupt
	PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
	IER |= M_INT3;
}

